A beneficial technology for three-dimensional (3D) integration employs vertical interconnects known as through silicon vias (TSVs). The TSVs may be formed using, for example, a via-first process or a via-middle process. In the via-first process, the TSVs are generally formed prior to complementary metal-oxide-semiconductor (CMOS) process and in the via-middle process the TSVs are generally formed in between the CMOS process and back-end-of line (BEOL) process.
Unfortunately, forming TSVs using either the via-first process or the via-middle process can be challenging and costly. Because of the high cost, improvements in 3D integration technology continue to be sought.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.